1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a method of forming sidewall spacers for gate electrode structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon a variety of factors, such as the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on, among other things, the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Historically, in field effect transistors, silicon dioxide has typically been used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high-speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include so-called high-k materials (k value greater than 10) that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the typical polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed. For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. As noted above, given that the gate length on modern transistor devices is 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a device would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from the PMOS transistors. The techniques employed in forming such nitride layers for selective channel stress engineering purposes are well known to those skilled in the art.
Typically, one or more sidewall spacers are formed adjacent the gate electrode structures of transistors for a variety of reasons, such as to protect the gate electrode materials, to insure that subsequent structures, such a metal silicide regions formed on the source and drain regions of a transistor, are formed a minimum distance away from the channel region of the device, etc. FIGS. 1A-1C depict a simplified view of an illustrative semiconductor device 100 at an early stage of manufacturing that is formed above a semiconducting substrate 10. In one illustrative embodiment, the semiconducting substrate 10 is comprised of silicon. The substrate 10 may have a variety of configurations, such the depicted silicon-on-insulator (SOI) structure having a bulk silicon layer 10A, a buried insulation layer 10B and an active layer 10C. The substrate 10 may also have a simple bulk silicon configuration. At the point of fabrication depicted in FIG. 1A, the semiconductor device 100, e.g., a transistor, includes a gate electrode structure 20 that includes a gate insulation layer 20A that may be made of, for example, silicon dioxide, a high-k gate insulation layer 20B, a metal layer 20C that may be made of, for example, titanium nitride, and a conductive layer 20D that may be made of, for example, polysilicon, amorphous silicon, etc. The gate electrode structure 20 may be made using techniques well known to those skilled in the art.
Also depicted in FIG. 1A are simplified depictions of sidewall spacers 22, 24, and 26 that are formed adjacent the gate electrode structure 20. In some cases, people within the industry may refer to the spacer 22 as “spacer 0”, whereas the combination of the spacers 24 and 26 may be referred to as “spacer 1.” Of course, additional spacers other than those depicted in FIG. 1A can be formed on the device 100 if needed or desired for the particular application. In general, each of the spacers 22, 24 and 26 is formed by depositing a layer of spacer material and thereafter performing an etching process to remove the undesired parts of such a deposited layer of spacer material. In one embodiment, the spacer 22 is made of silicon nitride and it has a thickness of 3-6 nm, the spacer 24 is made of silicon dioxide and it has a thickness of 2-4 nm, and the spacer 26 is made of silicon nitride and it has a thickness of 10-30 nm. These various spacers serve different purposes. For example, spacer 22, is provided to, among other things, physically protect one or more of the layers in the gate electrode structure 20 from attack during subsequent processing operations. In some cases, the spacer 22 may also be formed prior to performing a relatively heavy source-drain implant so as to properly position the implant region on a device, such as an NMOS transistor. In other cases the spacer 22 may be employed to properly locate a another structure of layer of material, such as silicon germanium, that may be grown in the source/drain regions of a PMOS transistor. The silicon dioxide L-shaped spacer 24 is typically provide to, in theory, protect the silicon nitride spacer 22 from subsequent etching processes that may attack the silicon nitride spacer 22, with the ultimate objective always being to insure the integrity of the silicon nitride spacer 22 so as to protect the gate electrode structure 20. The silicon nitride spacer 26, in combination with the L-shaped silicon dioxide spacer 26, may be employed to properly located metal silicide regions (not shown) on the source/drain regions that will be formed for the device 100.
One problem associated with the prior art spacer configuration disclosed above is that the silicon nitride spacer 22 can be undesirably attacked in subsequent etching process which can cause at least portions of the gate electrode structure 20 to likewise be subject to undesirable attacks or degradation. For example, if the integrity of the silicon nitride spacer 22 is compromised enough, the metal layer 20C, e.g., titanium nitride, may be subject to attack by subsequent etching operations performed to remove nitride based layers, like subsequent etching processes performed to remove all or part of the stressed nitride layers that are formed for channel stress engineering purposes. Additionally, if the metal layer 20C is exposed, oxygen may ingress into the metal layer 20C which may cause the resulting device 100 to exhibit a higher threshold voltage than would otherwise be desired, which can reduce device performance.
FIG. 1B depicts the device 100 after some subsequent processing operations have been performed and depicts an example where the overall height of the silicon nitride spacer 22 has been reduced during such process operations, thereby exposing a portion of the gate electrode structure 20. Typically, after the silicon nitride spacer 26 is formed, and the metal silicide regions (not shown) for the device 100 are formed on the source/drain regions (not shown), the silicon nitride spacer 26 is removed by performing an etching process. However, during this process, the upper surface 22S (see FIG. 1A) of the silicon nitride spacer 22 is also exposed to this etching process and therefore subject to attack. During the etching process performed to remove the silicon nitride spacer 26, the L-shaped silicon dioxide spacer 24 is intended to protect the silicon nitride spacer 22 from that etching process. However, for a variety of reasons, the L-shaped silicon dioxide spacer 24 is not always effective at performing this task. For example, the L-shaped silicon dioxide spacer 24 is relatively thin to begin with and uneven device topography, which is typically present, makes it difficult to form the L-shaped silicon dioxide spacer 24 such that it uniformly has the desired minimum thickness for protecting the silicon nitride spacer 22. Processing variations from tool to tool may also make forming the L-shaped silicon dioxide spacer 24 uniform and repeatable manner difficult.
FIG. 1C depicts the device 100 after it has be subject to further attack such as when the silicon nitride layers used for channel stress engineering purposes are selectively formed and removed from above the NMOS and PMOS devices on the substrate. In FIG. 1C, the degradation of the silicon nitride spacer 22 is such that the metal layer 20C, e.g., titanium nitride, is exposed to subsequent processing techniques and perhaps to oxygen ingress into the metal layer 20C, as mentioned above.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.